Messages – LU1QA-15

Found 158 packets. 0.002 packets/s on average over 79220 s. Query took 0.017 s. On average 504.6 s between packets.

APRS messages, acknowledgements (ack) and rejects (rej). Kept for 14 days.

2026-10-30 15:38:40 UTC: LU2QJL-7>LU1QA-15: Status 3141 {6

2026-10-30 15:24:11 UTC: LU2QJL-7>LU1QA-15: Repe off 3141 {5

2026-10-30 15:12:11 UTC: LU2QJL-7>LU1QA-15: Status 3141 {6

2026-10-30 15:08:12 UTC: LU2QJL-7>LU1QA-15: Status 3141 {6

2026-10-30 15:03:16 UTC: LU2QJL-7>LU1QA-15: Status 3141 {6

2026-10-30 15:00:01 UTC: LU2QJL-7>LU1QA-15: Status 3141 {6

2026-10-30 14:57:00 UTC: LU2QJL-7>LU1QA-15: Status 3141 {6

2026-10-30 14:57:00 UTC: LU2QJL-7>LU1QA-15: Repe off 3141 {5

2026-10-30 14:51:06 UTC: LU2QJL-7>LU1QA-15: Repe off 3141 {5

2026-10-30 14:50:23 UTC: LU2QJL-7>LU1QA-15: Status 3141 {6

2026-10-30 14:49:05 UTC: LU2QJL-7>LU1QA-15: Repe off 3141 {5

2026-10-30 14:48:22 UTC: LU2QJL-7>LU1QA-15: Status 3141 {6

2026-10-30 14:47:34 UTC: LU2QJL-7>LU1QA-15: Repe off 3141 {5

2026-10-30 14:46:52 UTC: LU2QJL-7>LU1QA-15: Status 3141 {6

2026-10-30 14:46:27 UTC: LU2QJL-7>LU1QA-15: Repe off 3141 {5

2026-10-30 14:45:59 UTC: LU2QJL-7>LU1QA-15: Status 3141 {4

2026-10-30 14:45:59 UTC: LU2QJL-7>LU1QA-15: Repe off 3141 {3

2026-10-30 14:44:03 UTC: LU1QA-15>LU2QJL-10: UT:2h T:40.1c RAM:27% DSK:39% CPU:41% SRV:FAIL:HLT PWR:OK

2026-10-30 14:44:00 UTC: LU1QA-15>LU2QJL-10: ack006

2026-10-30 14:43:58 UTC: LU2QJL-10>LU1QA-15: status 3141 {006

2026-10-30 14:43:33 UTC: LU1QA-15>LU2QJL-10: UT:2h T:40.1c RAM:27% DSK:39% CPU:42% SRV:FAIL:HLT PWR:OK

2026-10-30 14:43:30 UTC: LU1QA-15>LU2QJL-10: ack005

2026-10-30 14:43:28 UTC: LU2QJL-10>LU1QA-15: status 3141 {005

2026-10-30 14:42:54 UTC: LU1QA-15>LU2QJL-10: UT:2h T:40.1c RAM:27% DSK:39% CPU:47% SRV:FAIL:HLT PWR:OK

2026-10-30 14:42:51 UTC: LU1QA-15>LU2QJL-10: ack004

2026-10-30 14:42:50 UTC: LU2QJL-10>LU1QA-15: Status 3141 {004

2026-10-30 14:37:22 UTC: LU1QA-15>LU2QJL-10: ack003

2026-10-30 14:37:20 UTC: LU2QJL-10>LU1QA-15: St?[28~atus 3141 {003

2026-10-30 14:35:20 UTC: LU1QA-15>LU2QJL-10: UT:1h T:40.1c RAM:27% DSK:39% CPU:42% SRV:FAIL:HLT PWR:OK

2026-10-30 14:35:17 UTC: LU1QA-15>LU2QJL-10: ack002

2026-10-30 14:35:15 UTC: LU2QJL-10>LU1QA-15: status 3141 {002

2026-10-30 14:34:19 UTC: LU1QA-15>LU2QJL-10: UT:1h T:39.0c RAM:27% DSK:39% CPU:44% SRV:FAIL:HLT PWR:OK

2026-10-30 14:34:15 UTC: LU2QJL-10>LU1QA-15: Status 3141 {001

2026-10-30 14:32:54 UTC: LU2QJL-10>LU1QA-15: PWR:UVH,THRH

2026-10-30 14:32:53 UTC: LU2QJL-10>LU1QA-15: UT:1h T:36.9c RAM:26% DSK:40% CPU:56% SRV:FAIL:HLT

2026-10-30 14:32:50 UTC: LU2QJL-10>LU1QA-15: ack002

2026-10-30 14:32:44 UTC: LU1QA-15>LU2QJL-10: status 3141 {002

2026-10-30 14:32:12 UTC: LU1QA-15>LU2QJL-10: Repe reboot 3141 {001

2026-10-30 14:31:18 UTC: LU2QJL-10>LU1QA-15: PWR:UVH,THRH

2026-10-30 14:31:17 UTC: LU2QJL-10>LU1QA-15: UT:1h T:36.9c RAM:26% DSK:40% CPU:48% SRV:FAIL:HLT

2026-10-30 14:31:08 UTC: LU1QA-15>LU2QJL-10: status 3141 {001

2026-10-30 14:26:36 UTC: LU2QJL-7>LU1QA-15: Status 3141 {4

2026-10-30 14:26:34 UTC: LU2QJL-7>LU1QA-15: Repe off 3141 {3

2026-10-30 14:18:04 UTC: LU2QJL-7>LU1QA-15: Status 3141 {4

2026-10-30 14:18:03 UTC: LU2QJL-7>LU1QA-15: Repe off 3141 {3

2026-10-30 14:12:00 UTC: LU2QJL-7>LU1QA-15: Status 3141 {4

2026-10-30 14:11:40 UTC: LU2QJL-7>LU1QA-15: Repe off 3141 {3

2026-10-30 14:09:41 UTC: LU2QJL-7>LU1QA-15: Status 3141 {4

2026-10-30 14:09:14 UTC: LU2QJL-7>LU1QA-15: Repe off 3141 {3

2026-10-30 14:08:14 UTC: LU2QJL-7>LU1QA-15: Repe off 3141 {3