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Raw packets – EA1GTX-10

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Found 158 packets. 0.001 packets/s on average over 172214 s. Query took 0.021 s.

2026-10-31 03:18:57 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-31 03:03:57 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-31 02:48:57 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-31 02:33:57 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-31 02:18:56 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-31 01:48:56 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-31 01:33:56 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-31 01:18:56 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-31 01:03:32 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-31 00:48:32 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-31 00:33:32 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-31 00:18:32 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-31 00:03:32 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 23:48:32 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 23:18:31 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 22:48:07 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 22:33:06 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 22:18:06 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 21:48:06 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 21:33:06 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 21:18:06 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 21:03:06 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 20:48:06 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 20:03:04 UTC: EA1GTX-10>APLRG1,WIDE1-1,QB6N0,qAR,ED1ZBH-10:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 19:48:04 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 19:33:04 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 19:18:04 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 19:03:04 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 18:48:04 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 18:33:04 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 18:18:04 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 18:03:03 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 17:48:03 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 17:33:03 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 17:18:03 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 17:03:03 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 16:48:03 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 16:33:03 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 16:18:03 UTC: EA1GTX-10>APLRG1,WIDE1-1,QB6N0,qAR,ED1ZBH-10:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 16:03:03 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 15:48:03 UTC: EA1GTX-10>APLRG1,WIDE1-1,QB6N0,qAR,ED1ZBH-10:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 15:33:03 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 15:18:03 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 15:03:03 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 14:33:06 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 14:17:59 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 14:02:59 UTC: EA1GTX-10>APLRG1,WIDE1-1,QB5M9,qAR,ED1ZBH-10:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 13:47:59 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 13:02:59 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS
2026-10-30 12:47:59 UTC: EA1GTX-10>APLRG1,WIDE1-1,qAO,EA1CUE-2:!L9(VWL\]1& GTrives LoRa APRS

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