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Исходные пакеты – SR8ULZ-1

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Обнаружено 131 пакетов. 0.001 пакетов в сек. среднее значение за 171006 сек. Просмотр занимает 0.026 сек.

2026-10-31 08:04:19 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|+O#x";"9!!!!|
2026-10-31 07:34:18 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|+N#v":"8!!!!|
2026-10-31 07:04:17 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|+M#t"9"7!!!!|
2026-10-31 06:34:16 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|+L#r"8"6!!!!|
2026-10-31 06:04:16 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|+K#p"7"5!!!!|
2026-10-31 05:34:15 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|+J#n"6"4!!!!|
2026-10-31 05:04:15 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|+I#l"5"3!!!!|
2026-10-31 05:04:14 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:>System booted W2 TX&RX 434.855MHz 1200bps
2026-10-31 05:04:13 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10::SR8ULZ-1 :EQNS.0,1,0,0,1,0,0,1,0,0,0.01,0,0,0.02,0
2026-10-31 05:04:09 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10::SR8ULZ-1 :UNIT.Count,Count,Count,VDC,VDC
2026-10-31 05:04:05 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10::SR8ULZ-1 :PARM.TX,RX,Digi,V_Bat,V_Ext
2026-10-31 05:04:03 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:>Scheduled Reboot
2026-10-31 04:34:21 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|+G#f"4"2!!!!|
2026-10-31 04:04:20 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|+F#d"3"1!!!!|
2026-10-31 03:34:19 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|+E#b"2"0!!!!|
2026-10-31 03:04:19 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|+D#`"1"/!!!!|
2026-10-31 02:34:19 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|+C#^"0".!!!!|
2026-10-31 02:04:17 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|+B#\"/"-!!!!|
2026-10-31 01:34:17 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|+A#Z".",!!!!|
2026-10-31 01:04:17 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|+@#X"-"+!!!!|
2026-10-31 00:34:16 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|+?#V","*!!!!|
2026-10-31 00:04:15 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|+>#T"+")!!!!|
2026-10-30 23:34:14 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|+=#R"*"(!!!!|
2026-10-30 23:04:14 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|+<#P")"'!!!!|
2026-10-30 23:04:13 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:>System booted W2 TX&RX 434.855MHz 1200bps
2026-10-30 23:04:12 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10::SR8ULZ-1 :EQNS.0,1,0,0,1,0,0,1,0,0,0.01,0,0,0.02,0
2026-10-30 23:04:08 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10::SR8ULZ-1 :UNIT.Count,Count,Count,VDC,VDC
2026-10-30 23:04:05 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10::SR8ULZ-1 :PARM.TX,RX,Digi,V_Bat,V_Ext
2026-10-30 23:04:02 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:>Scheduled Reboot
2026-10-30 22:34:20 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|"3#J"("&!!!!|
2026-10-30 22:04:19 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|"2#H"'"%!!!!|
2026-10-30 21:34:18 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|"1#F"&"$!!!!|
2026-10-30 21:04:18 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|"0#D"%"#!!!!|
2026-10-30 20:34:17 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|"/#B"$""!!!!|
2026-10-30 20:04:17 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|".#@"#"!!!!!|
2026-10-30 19:34:16 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|"-#>""!{!!!!|
2026-10-30 19:04:16 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|",#<"!!z!!!!|
2026-10-30 18:34:16 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|"+#:!{!y!!!!|
2026-10-30 18:04:14 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|"*#8!z!x!!!!|
2026-10-30 17:34:13 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|")#6!y!w!!!!|
2026-10-30 17:04:13 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|"(#4!x!v!!!!|
2026-10-30 17:04:12 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:>System booted W2 TX&RX 434.855MHz 1200bps
2026-10-30 17:04:11 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10::SR8ULZ-1 :EQNS.0,1,0,0,1,0,0,1,0,0,0.01,0,0,0.02,0
2026-10-30 17:04:07 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10::SR8ULZ-1 :UNIT.Count,Count,Count,VDC,VDC
2026-10-30 17:04:04 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10::SR8ULZ-1 :PARM.TX,RX,Digi,V_Bat,V_Ext
2026-10-30 17:04:02 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:>Scheduled Reboot
2026-10-30 16:34:19 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|*Q#.!w!u!!!!|
2026-10-30 16:04:18 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|*P#,!v!t!!!!|
2026-10-30 15:34:18 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|*O#*!u!s!!!!|
2026-10-30 15:04:17 UTC: SR8ULZ-1>APLRFD,WIDE2-1,qAR,SQ5LTL-10:!L4FfqT(E"# GLoRa APRS Digi Ulez|*N#(!t!r!!!!|

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