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Raw packets – XE2RCS-31

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Found 90 packets. 0.001 packets/s on average over 165601 s. Query took 0.019 s.

2026-10-30 19:42:09 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2FAA-13:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.06V
2026-10-30 19:12:09 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2FAA-13:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.03V
2026-10-30 18:42:09 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2FAA-13:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.05V
2026-10-30 18:12:09 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2FAA-13:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.06V
2026-10-30 17:42:09 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.06V
2026-10-30 17:12:09 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2FAA-13:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.04V
2026-10-30 16:42:08 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.05V
2026-10-30 16:12:09 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.05V
2026-10-30 15:42:08 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.05V
2026-10-30 15:12:15 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.05V
2026-10-30 14:42:09 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.05V
2026-10-30 14:12:08 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.05V
2026-10-30 13:12:08 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.03V
2026-10-30 12:42:08 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.04V
2026-10-30 12:12:08 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.04V
2026-10-30 11:42:08 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.04V
2026-10-30 11:12:08 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.04V
2026-10-30 10:42:08 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.05V
2026-10-30 10:12:09 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.04V
2026-10-30 09:42:08 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.03V
2026-10-30 09:12:08 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.03V
2026-10-30 08:42:09 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.04V
2026-10-30 07:42:07 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.05V
2026-10-30 07:12:07 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.04V
2026-10-30 06:42:08 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.06V
2026-10-30 06:12:08 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.04V
2026-10-30 05:42:08 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.04V
2026-10-30 05:12:07 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.05V
2026-10-30 04:42:07 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.03V
2026-10-30 04:12:07 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.05V
2026-10-30 03:42:07 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.04V
2026-10-30 03:12:07 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.05V
2026-10-30 02:42:07 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.04V
2026-10-30 02:12:07 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.03V
2026-10-30 01:42:07 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.03V
2026-10-30 01:12:08 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.04V
2026-10-30 00:42:07 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.04V
2026-10-30 00:12:16 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:>https://github.com/richonguzman/LoRa_APRS_iGate 2024.06.28
2026-10-30 00:12:09 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.04V
2026-10-29 23:42:09 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.03V
2026-10-29 23:12:09 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.04V
2026-10-29 22:42:09 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.04V
2026-10-29 22:12:09 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.04V
2026-10-29 21:42:09 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.04V
2026-10-29 21:12:09 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.03V
2026-10-29 20:42:09 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.04V
2026-10-29 20:12:09 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.04V
2026-10-29 19:42:09 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.05V
2026-10-29 18:42:08 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.05V
2026-10-29 18:12:08 UTC: XE2RCS-31>APLRG1,WIDE1-1,qAR,XE2RCS-21:!LA_%=4{I`# xGLoRa APRS PENITENTE Batt=5.05V

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